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PM7380-PI IC产品库存

PM7380-PI:FRAME ENGINE AND DATA LINK MANAGER 32P672
库存编号:
81530
产品型号:
PM7380-PI
厂商:
PMC
封装:
PBGA
库存数量:
63
参考价:
0
起订量:
1
点击率:
566
PDF搜索:
下载
立即订购:
PM7380-PI
联系电话:
0755-82516777

PM7380-PI 产品描述

FRAME ENGINE AND DATA LINK MANAGER 32P672

PM7380-PI 产品简介

FEATURES
Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral
Component Interconnect (PCI) Revision 2.1 bus for configuration, monitoring
and transfer of packet data, with an on-chip DMA controller with scatter/
gather capabilities.
Supports up to 672 bi-directional HDLC channels assigned to a maximum of
32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are
grouped into 4 logical groups of 8 links. A common clock and a type 0 frame
pulse is shared among links in each logical group. The number of time-slots
assigned to an HDLC channel is programmable from 1 to 32.
Supports up to 672 bi-directional HDLC channels assigned to a maximum of
8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a
common clock and a type 0 frame pulse. The number of time-slots assigned
to an HDLC channel is programmable from 1 to 128.
Supports up to 672 bi-directional HDLC channels assigned to a maximum of
32 channelised T1/J1 or E1 links. The number of time-slots assigned to an
HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for
E1).
Supports up to 32 bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link, subject to a maximum aggregate link clock
rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a
clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support a
clock rate of up to 10 MHz.
Supports three bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running
at 45 MHz.
Supports a mix of up to 32 channelised, unchannelised and H-MVIP links,
subject to the constraint of a maximum of 672 channels and a maximum
aggregate link clock rate of 64 MHz in each direction.
Links configured for channelised T1/J1/E1 or unchannelised operation
support the gapped-clock method for determining time-slots which is
backwards compatible with the FREEDM-8 and FREEDM-32 devices.
For each channel, the HDLC receiver supports programmable flag sequence
detection, bit de-stuffing and frame check sequence validation. The receiver>

PM7380-PI 产品图片

PM7380-PI 相关库存

型号 厂商 封装 描述 资料 采购
PM7380-PI PMC PBGA FRAME ENGINE AND DATA LINK MANAGER 32P672


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联系方式

联系时间:每周一至周五
   上午9.00至11:45,
   下午13:30至17.50
联系电话:
   0755-82516668,82516777
联系传真:
   0755-82516669
业务联系QQ:
   QQ一:882222 ,QQ二:308917
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